MRAM is a nonvolatile memory technology that uses magnetization to represent stored data, in contrast to older RAM technologies that use electronic charges to store data. One primary benefit of MRAM is that it retains the stored data in the absence of electricity, i.e., it is a nonvolatile memory. Generally, MRAM includes a large number of magnetic cells formed on a semiconductor substrate, where each cell represents one data bit. A bit is written to a cell by changing the magnetization direction of a magnetic element within the cell, and a bit is read by measuring the resistance of the cell (low resistance typically represents a “0” bit and high resistance typically represents a “1” bit).
FIG. 1 is a schematic perspective view of a simplified MRAM device 100, and FIG. 2 and FIG. 3 are schematic perspective views of a simplified MRAM cell 102. Although MRAM device 100 includes only nine cells 102, a practical MRAM device will typically include millions of cells. Generally, cell 102 includes an upper ferromagnetic layer 104, a lower ferromagnetic layer 106, and an insulating layer 108 between the two ferromagnetic layers. In this example, upper ferromagnetic layer 104 is the free magnetic layer because the direction of its magnetization can be switched to change the bit status of cell 102. Lower ferromagnetic layer 106, however, is the fixed magnetic layer because the direction of its magnetization does not change. When the magnetization in upper ferromagnetic layer 104 is parallel to the magnetization in lower ferromagnetic layer 106 (see FIG. 2), the resistance across cell 102 is relatively low. When the magnetization in upper ferromagnetic layer 104 is anti-parallel to the magnetization in lower ferromagnetic layer 106 (see FIG. 3), the resistance across cell 102 is relatively high. The data (“0” or “1”) in a given cell 102 is read by measuring the resistance of the cell 102. In this regard, electrical conductors 110/112 attached to the cells 102 are utilized to read the MRAM data.
FIG. 4 is a schematic representation of a conventional switching technique for an MRAM cell 120 having a free magnetic layer 122, an insulating layer 124, and a fixed magnetic layer 126. The orientation of magnetization in free magnetic layer 122 can point in one of two directions (left or right in FIG. 4), while the orientation of fixed magnetic layer 126 can only point in one direction (right in FIG. 4). The orientation of the magnetization in free magnetic layer 122 rotates in response to current 127 flowing in a digit line 128 and in response to current 129 flowing in a write line 130. FIG. 4 depicts the situation where the current in digit line 128 is flowing out of the page, and the current in write line 130 is flowing from left to right, which will cause the magnetization in free magnetic layer 122 to switch from parallel to anti-parallel to the magnetization in fixed magnetic layer 126. In a typical MRAM, the orientation of the bit is switched by reversing the polarity of the current 129 in the write line 130 while keeping a constant polarity of the current 127 in the digit line 128.
The traditional MRAM switching technique depicted in FIG. 4 has some practical limitations, particularly when the design calls for scaling the bit cell to smaller dimensions. For example, since this technique requires two sets of magnetic field write lines, the array of MRAM cells is susceptible to bit disturbs (i.e., neighboring cells may be unintentionally altered in response to the write current directed to a given cell). Furthermore, decreasing the physical size of the MRAM cells results in lower magnetic stability against magnetization switching due to thermal fluctuations. The stability of the bit can be enhanced by utilizing a magnetic material for the free layer with a large magnetic anisotropy and therefore a large switching field, but then the currents required to generate a magnetic field strong enough to switch the bit are impractical in real applications.
Transmission mode spin-transfer switching is another technique for writing MRAM bit data. Writing bits using the spin-transfer interaction can be desirable because bits with a large coercivity (Hc) in terms of magnetic field induced switching (close to 1000 Oe) can be switched using only a modest current, e.g., less than 5 mA. The higher Hc results in greater thermal stability and less possibility for disturbs. FIG. 5 is a schematic representation of a transmission mode spin-transfer switching technique for an MRAM cell 150 having a first magnetic layer 152, a nonmagnetic layer 154, and a second magnetic layer 156. In this technique, the write current 157 actually flows through cell 150 (with the arrow representing the direction of the electron flow). According to the spin-transfer effect, the electrons in the write current become spin-polarized after they pass through first magnetic layer 152. In this regard, first magnetic layer 152 functions as a polarizer. The spin-polarized electrons cross the nonmagnetic layer 154 and, through conservation of angular momentum, impart a torque on second magnetic layer 156. This torque causes the orientation of magnetization in second magnetic layer 156 to be parallel to the orientation of magnetization in first magnetic layer 152. The parallel magnetizations will remain stable until a write current of opposite direction switches the orientation of magnetization in second magnetic layer 156 to be anti-parallel to the orientation of magnetization in first magnetic layer 152.
The transmission mode spin-transfer switching technique requires relatively low power (compared to the conventional switching technique), virtually eliminates the problem of bit disturbs, results in improved data retention, and is desirable for small scale applications. In practice, however, this technique is difficult to implement in a memory array because the write current must flow through the magnetic tunnel junction embodied in the cell. This negatively affects reliability of the MRAM cells and requires the use of larger write transistors at each bit location that are capable of producing the necessary currents, which is incompatible with high-density applications.
Accordingly, it would be desirable to have a practical MRAM architecture that enables an ultra-dense, low power, MRAM device. In addition, it would be desirable to have a practical and selective write technique for a spin-transfer based MRAM array, where the write current does not flow through the MRAM cells. Furthermore, other desirable features and characteristics of the invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.